Flash memory is one of the segments of nonvolatile memory devices. The device includes a floating gate to store charges and an element for electrically placing charge on and removing the charges from the floating gate. One of the applications of flash memory is BIOS for computer. Typically, the high-density nonvolatile memories can be applied as the mass storage of portable handy terminals, solid state camera and PC cards. That is because that the nonvolatile memories exhibit many advantages, such as a fast access time, low power dissipation, and robustness. The formation of nonvolatile memories toward the trends of low supply power and fast access, because these requirements are necessary for the application of the mobile computing system. One important key parameters of high performance memory is capacitive-coupling ratio. Various nonvolatile memories have been disclosed in the prior art. For example, Mitchellx has proposed EPROMs with self-aligned planar array cell. In this technique, buried diffusion self-aligned to the floating gate avalanche injection MOS transistor are used for the bit lines. Cross point array technology has been disclosed. The self-aligned source and drain will allow this device to be optimized even further for programming speed. See A. T. Mitchellx, "A New Self-Aligned Planar Cell for Ultra High Density EPROMs", IEDM, Tech. pp. 548-553, 1987.
An article proposed by Kevin et al. relates to the formation of the stacked floating gate devices using TiN as a control gate. This is discussed in 1997 Symposium on VLSI Technology Digest of Technical Papers. This structure includes the use of TiN cladding by inserting a high quality oxide between the poly-gate and the TiN cladding. Youichi et al. proposed a structure with Ta.sub.2 O.sub.5 /SiO.sub.2 gate insulator with TiN gate technology. This devices can break through the limitation of a thin SiO.sub.2 gate insulator with a poly-Si electrode. The Ta.sub.2 O.sub.5 /SiO.sub.2 structure can provide a stable interface, thus the reliability of the device is improved. In the research, the device will exhibit high drive current and good sub-threshold slope. The Ta.sub.2 O.sub.5 /SiO.sub.2 gate insulator with an equivalent oxide thickness of less than 5 nm. Therefore, it is a proper structure to replace the oxide as the gate insulator for smaller devices. This structure is proposed in 1997 Symposium on VLSI Technology Digest of Technical Papers.
Metal oxide of high dielectric has been researched to take over the silicon dioxide as the gate dielectric. Recently, prior art proposed a TiO.sub.2 film as a gate dielectric to replace the oxide. JVD nitride layer, which refers to the nitride formed by jet vapor deposition, is used as an under layer of TiO.sub.2 for MIS (metal-insulator-silicon) structure. Typically, the interfacial layer is a serious issue of the metal oxide dielectric layer formed on the silicon material. The effective dielectric constant of the MIS capacitor is degraded due to the interfacial layer. The main reason for forming the interfacial layer is in the initial step of deposition. A research in IEDM, proposed by B. Hc et al., p. 1038 (1998), entitled "A 1.1 nm Oxide Equivalent Gate Insulator Formed Using on TiO.sub.2 Nitride Silicon". B. He et al., has approached that there exist an inter diffusion problem between the silicon and high k dielectric layer. During the annealing, inter-diffusion of Si, Ti and O occurred. The interfacial layer consists of Ti.sub.x Si.sub.y O.sub.z. Thus, a barrier layer is needed in the metal/high k/Si (MIS) structure to overcome the inter diffusion problem. The JVD nitride is an effect barrier layer to suppress the inter diffusion problem. Please refer to a further article "Effect of Barrier Layer on the Electrical and Reliability Characteristic of High-k Gate Dielectric films", IEEE, 1998, Yongjoo et al., p. 797. The use of JVD as an oxidation barrier can obtain thin equivalent oxide thickness (ETO). As known in the art, the interfacial layer increases ETO and the inter-diffusion causes the trap generation. In the paper of Yongjoo, it mentioned that ETO of TiO.sub.2 /JVD nitride/Si structure is thinner than the TiO.sub.2 /Si structure. Thus, the JVD nitride is an effect barrier layer to suppress the formation of interfacial layer.
Furthermore, the nitride made by the JVD exhibits excellent electrical properties. The JVD nitride has lower leakage current than the one of oxide and it has high resistant to boron penetration. Please refer to an article entitled "Ultra-thin Silicon Nitride Gate Dielectric for Deep-Sub-Micron CMOS Device", Mukesh Khare et al., 1997 Symposium on VLSI Technology Digest of Technical Papers.